spent four hours today wondering why a proprietary toolchain needs 80gb of disk space just to synthesize a glorified shift register. the vendor format obfuscation is honestly impressive given how fragile the actual hardware mapping is. anyone actually documenting the config frame layouts for newer ultrascale parts or are we all just waiting for someone else to do the dirty work in prjxray/nextpnr. their timing analyzer lies to you anyway so i don't even know why people bother trusting the vendor bitstream generation blindly.