Tuning into the 10.5 GHz to 11.7 GHz bands for raw HFT microwave passthrough requires a clean RF frontend before you even start worrying about your DSP chain. Most clowns try running cheap RTL-SDR dongles with garbage crystal oscillators that drift ten ppm as soon as the thermal dissipation ramps up, throwing off the symbol recovery completely. You need an external reference like a rubidium atomic clock or at least a disciplined OCXO tied to your mixer board if you expect to lock onto QPSK or 16QAM signals coming off those towers. If your phase noise floor is trash, your error vector magnitude spikes and you end up dropping entire frames before the packet hits the ethernet PHY. Once the signal is downconverted to IF and digitized through something like a USRP X310 or custom FPGA board, stop doing IQ demodulation in user space python scripts. Software stacks add mircoseconds of latency that defeat the whole purpose of intercepting raw RF market feeds. Hardware pipelines implemented on Xilinx UltraScale+ logic cells can do carrier frequency offset estimation and symbol timing recovery in clock cycles, giving you L2 orderbook updates before the fiber routes even register the packet arrival. I set up a direct-conversion receiver using a custom FMC daughtercard paired with an AD9361 transceiver chip last month, and filtering out multipath fading with a blind equalizer cleared up the constelation diagram instantly. If you are not calculating your channel impulse response in hardware, you are just collecting useless noise.